The anti-undershoot circuit for single stage and multistage circuits described in U.S. patent application Ser. No. 327,348 incorporates an anti-overshoot circuit transistor element AUCT having the primary current path first and second nodes coupled in an anti-undershoot circuit. The AUCT is coupled between a current source such as a V.sub.CC output supply PV and an output ground PG and through the output ground lead inductance to the external ground and output capacitance. An AUCT control circuit is arranged for establishing transient flow of a sacrificial current through the AUCT primary current path from the output supply current source and through the output ground lead inductance to external ground following transition from high to low potential at the output. The AUCT parameters and dimensions are constructed to provide selected resistance in the primary current path in the conducting state for dissipating undershoot electrical energy stored in the output ground lead inductance thereby damping ground potential undershoot and subsequent ringing in the output ground.
The basic elements of an anti-overshoot circuit similarly include an off chip power supply current source for supplying the transient sacrificial current, an anti-overshoot transistor element AOCT, and a control circuit for initiating transient flow of sacrificial current through the anti-overshoot circuit transistor element AOCT following transition from low to high potential at the output. The anti-overshoot circuit couples the parasitic supply lead inductance in the sacrificial current path along with dissipating resistance. Parasitic tank circuit energy stored in the supply lead inductance is thereby dissipated in the dissipating resistance. This dissipating resistance is typically provided by the channel resistance of the anti-overshoot circuit transistor AOCT in a manner similar to the AUCT.
A low noise circuit described in the related U.S. patent application Ser. No. 327,348 is illustrated in FIG. 1. FIG. 1 of the present patent application is the same as FIG. 24 of U.S. Pat. No. 327,348. The combined low noise circuit is incorporated in a tristate output stage of, for example, an octal buffer line driver. This tristate output buffer incorporates both an anti-bounce circuit for suppressing ground bounce and an anti-undershoot circuit for rapidly dissipating ground undershoot energy. The tristate output buffer of FIG. 1 is noninverting so that a high potential level data signal appears at the output V.sub.OUT after a high level data signal is applied at the input V.sub.IN. This is accomplished by two stages of current amplification with inversion, the first stage including the complementary pair of MOS transistors P1 and N1, and a second stage which includes the output pullup transistor element P2 and pulldown transistor element N2. The pulldown transistor N2 is shown in a form which permits user selection of the size of transistor N2.
The anti-undershoot circuit incorporates a PMOS anti-undershoot circuit transistor AUCT with its primary current path operatively coupled between the output supply PV and through the output V.sub.OUT to the output ground PG for establishing transient sacrificial current flow following transition from high to low potential at the output V.sub.OUT. The channel width of the AUCT, for example 240 microns, is selected to provide the desired resistance for critically damping and rapidly dissipating ground undershoot energy. The AUCT is normally not conducting because its PMOS gate is supplied with charge by the output supply PV through the AUCT control path resistance CPR and the anti-undershoot switch transistor AUST. In this example the CPR is provided by a gate grounded PMOS transistor with small channel width of for example 14 microns and length of 21 microns providing the desired resistance to current during charging and discharge of the gate of the AUCT.
The anti-undershoot switch transistor AUST is normally conducting with its gate coupled to a ground undershoot detector GUD circuit such as the circuit of FIG. 2 which provides a ground undershoot signal GUS normally at low potential in the absence of detected ground undershoot. A transient GUS of high potential is provided during occurrence and detection of ground undershoot in excess of the threshold differential of the GUD circuit.
The gate of the AUCT is also coupled to ground via the output V.sub.OUT by two logic condition transistors, a data input condition transistor ICT1 and a data output condition transistor OCT. As long as either of the NMOS transistors ICT1 and OCT is off, the charge at the gate of the AUCT cannot escape and the AUCT remains nonconducting.
During normal operation of the tristate output buffer in the bistate mode, enabled by a high level OE signal, and with a high level data signal at the output V.sub.OUT, the output condition network OCN delivers a high level signal charging the gate of NMOS output condition transistor OCT. The OCT is therefore already conducting. Upon receipt of a low level data signal at the input V.sub.IN, the inverting data enable network or data input network DIN charges the gate of input condition transistor ICT1 so that ICT1 also becomes conducting. During the transition of V.sub.OUT to a low level, the now conducting logic condition transistors ICT1 and OCT discharge the gate of the AUCT for transient flow of sacrificial current through the AUCT primary current path. It is noted that as long as the output device is in the bistate mode of operation with a high level OE signal, the output enable condition transistor OECT1 is not conducting and does not interfere in the operation of the AUCT. In the high impedance third state the OECT1 functions as a tristate control transistor turning off the AUCT.
Following the propagation delay through the output buffer and transition of the output V.sub.OUT from high to low potential, the network OCN turns off the output condition transistor OCT. As a result current flow from the output power supply PV begins to charge the gate of the AUCT through the CPR and AUST. The control path resistance CPR slows the charging of the gate of PMOS transistor AUCT therefore delaying the turn off of AUCT permitting the transient flow of sacrificial current through the primary conducting path of the AUCT following transition from high to low potential at the output V.sub.OUT.
If a ground undershoot event is detected a high level transient GUS turns off the switch transistor AUST increasing resistance in the path of current charging the gate of the AUCT further suppressing or retarding the turn off of sacrificial current flow. The sacrificial current flow is therefore prolonged during the transient occurrence of the detected ground undershoot event.
The sacrificial current flow I.sub.AUCT rises during the transition from high to low potential at the output V.sub.OUT and continues following the transition until the gate of the AUCT is charged. With the AUST interposing a high resistance for the duration of a transient GUS, the transient I.sub.AUCT is prolonged for further dissipation of ground undershoot energy. An advantage of coupling the AUCT to the output through the OCT and OCN is that the OCN and OCT prevent a fast rise in current through the primary current path of the AUCT and instead produce a more gradual concave rise time. Avoiding the fast rise avoids further disruption, noise and ringing in the power supply circuit and reduces power consumption.
The anti-overshoot circuit embodiments of U.S. Ser. No. 327,348 operate in a similar manner. However, an anti-overshoot circuit transistor element AOCT initiates sacrificial current flow in an anti-overshoot circuit following transition from low to high potential and turn on of the output pullup transistor element P2 at the output. While the anti-overshoot circuit is not shown in the circuit example of FIG. 1, it is illustrated in other circuit figures of U.S. Ser. No. 327,348.
An anti-bounce circuit for the tristate output buffer of FIG. 1 incorporates the tristate control transistors, PMOS transistor P7 and NMOS transistor N7, as the anti-bounce transistor elements ABT of the anti-bounce circuit. The TCT's P7 and N7 are normally conducting in the bistate mode of operation presenting only a very low resistance to the propagation of data signals through the buffer. Upon detection of a ground bounce event by a ground bounce detector GBD circuit such as the circuit of FIG. 3, a transient ground bounce signal GBS of low potential is applied at the GBS input terminal drawing the current flow through the anti-bounce logic condition transistors ICT2 and OECT2. In the bistate mode of operation with a high level OE signal, the output enable condition transistor OECT2 is conducting. Similarly, with the appearance of a low level signal at the input V.sub.IN the network DIN delivers a high level signal to input condition transistor ICT2 so that it also is conducting. A low potential is therefore applied at the gate of anti-bounce NMOS transistor element N7 while a high level potential is applied at the gate of the anti-bounce PMOS transistor element P7.
Both the ABT's P7 and N7 are in the control path circuit of the pulldown transistor N2 and the transient turn off of transistors P7 and N7 increases resistance suppressing turn on of the pulldown transistor element N2 for the duration of the detected ground bounce event and ground bounce signal GBS. Upon correction of the ground bounce the GBS input signal rises to the normal high condition blocking current flow through the anti-bounce logic condition transistors ICT2 and OECT2. As a result the ABT's P7 and N7 conduct once again completing the turn on of pulldown transistor N2 and the transition from high to low potential at the output V.sub.OUT. The TCTs P9 and N9 remain nonconducting during the bistate mode of operation with a high level OE signal and do not interfere in the operation of the anti-bounce circuit or the propagation through the output buffer.
A ground undershoot detector GUD circuit with two stages of current amplification and inversion for use with the circuit of FIG. 1 is illustrated in FIG. 2. FIG. 2 of the present patent application is the same as FIG. 10 of U.S. Ser. No. 327,348. A ground undershoot event in excess of the voltage threshold detection level between the noisy output ground lead branch PG and the quiet internal ground lead branch QG of a split lead is detected by the GUD transistor element N3 which is combined with complementary PMOS transistor P3. Transistor P3 is normally conducting and the output of the first stage N3, P3 is normally high except during transient occurrence of a detected ground undershoot event when the output of the first stage is at low potential. A second inverting stage 40 is added so that the final ground undershoot signal output GUS is high during a ground undershoot event.
A ground bounce detector GBD circuit providing two stages of current amplification generating a ground bounce signal GBS for use with the circuit in FIG. 1 is illustrated in FIG. 3. FIG. 3 of the present patent application corresponds with FIG. 7 of U.S. Ser. No. 327,348. The basic ground bounce detector transistor element and first stage of current amplification is provided by NMOS transistor N3 in combination with the complementary PMOS transistor P3. A ground bounce event in excess of the voltage threshold detection level between the noisy output ground lead branch PG and quiet internal ground lead branch QG of a split lead is detected by the NMOS transistor element N3. When transistor N3 is conducting during a ground bounce event, complementary transistor P3 is nonconducting and acts as a high resistance. The NMOS transistor pair N4, N5 provides a noninverting stage of current amplification for the final GBS of low potential.
More generally U.S. patent. application Ser. No. 327,348 provides an anti-noise circuit for dissipating parasitic tank circuit energy causing ground undershoot and V.sub.CC overshoot in the power rails of an integrated circuit output stage with switching output transistor elements. The output power rails include ground and supply output power rails characterized by lead inductance. As result the power rails are subject to power rail noise upon switching of the output transistor elements.
The anti-noise circuit for dissipating parasitic tank circuit energy broadly includes a current source for sourcing a transient sacrificial current and a dissipating resistance. The anti-noise circuit couples the current source, dissipating resistance, and power rail lead inductance in a sacrificial current path. A control circuit initiates the transient sacrificial current flow in the sacrificial current path following switching of an output transistor for dissipating parasitic tank circuit energy.
In the case of an anti-undershoot circuit, the power rail of interest is the ground rail and the sacrificial current path and dissipating resistance are provided by the anti-undershoot circuit transistor element AUCT. In the case of an anti-overshoot circuit the power rail of interest is the supply rail and the transient sacrificial current path and dissipating resistance are provided by the anti-overshoot transistor element AOCT. Furthermore, the same transistor can serve as both the AUCT and AOCT. Finally, the control circuit can be one of a variety of circuits to initiate sacrificial current flow through the AUCT/AOCT in response to detection of transient undershoot or overshoot voltages, a switching event at the input of the output stage, a switching event at the output of the output stage, or a combination of these circuit events.
U.S. Ser. No. 327,348 also contemplates a variety of low noise circuits incorporating the ground noise detector, supply noise detector, anti-ground bounce circuit, anti-V.sub.CC droop circuit, anti-ground undershoot circuit, and anti-V.sub.CC overshoot circuit in any of a variety of permutations and combinations.
While the anti-noise circuit and in particular the anti-undershoot and anti-overshoot circuit of U.S. Ser. No. 327,348 provides satisfactory operation in the low and intermediate frequency integrated circuit operating range, limitations are encountered in faster ICs operating for example in the 20-70 mhz range. The prolonged sacrificial current for dissipating parasitic tank circuit energy either in the form of undershoot or overshoot limits the speed of operation of the integrated circuit device, degrades the output characteristics, and increases dynamic power requirements.